This invention relates to Silicon On Insulator (SOI) Devices and in particular to a cell stability test method and therefore useful for weak SOI memory cell testing.
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Within IBM tests not yet published have been developed for memory cells manufactured with SOI technologies which extended the wordline pulse width of the memory beyond the end of the cycle to stress the cell in a half word select state. Simulation analysis has shown that this is a worst condition for this type of instability.
One such unpublished test method is disclosed in co-pending application by Aipperspach et al., filed Apr. 19, 2000, Ser. No. 09/552,410 and assigned to IBM and entitled xe2x80x9cSTABILITY TEST FOR SILICON ON INSULATOR SRAM MEMORY CELLS UTILIZING BITLINE PRECHARGE STRESS OPERATIONS TO STRESS MEMORY CELLS UNDER TESTxe2x80x9d describing an apparatus, program product, and method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) to introduce switching history effects to a memory cell during testing to stress the memory cell such that a reliable determination of stability may be made. In that disclosed development stress is applied to a memory cell through the use of a bitline precharge stress operation, which utilizes the bitline pairs coupled to a memory cell to attempt to flood the memory cell with charge and thereby attempt to cause the memory cell to unexpectedly switch state. The bitline precharge stress operation is performed immediately after the memory cell has been switched to one state after being maintained in an opposite state for a length of time that is sufficient to introduce switching history effects to the memory cell. While a bitline precharge operation may be implemented separate from any write operation, the bitline precharge stress operation may also be incorporated into a write operation through delaying the deassertion of the wordline that occurs in a conventional write operation until after initiation of the bitline precharge operation that conventionally occurs near the end of such a write operation. Within that described application filed Apr. 19, 2000, Ser. No. 09/552,410 and assigned to IBM and entitled xe2x80x9cSTABILITY TEST FOR SILICON ON INSULATOR SRAM MEMORY CELLS UTILIZING BITLINE PRECHARGE STRESS OPERATIONS TO STRESS MEMORY CELLS UNDER TESTxe2x80x9d there is disclosed a method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) comprising: (a) introducing switching history effects to an SOI SRAM memory cell by maintaining the memory cell in a first state for a period of time, the memory cell including a pair of pass gates respectively coupled to a pair of bitlines and activated by a wordline; (b) setting the memory cell to a second state after introducing the switching history effects; (c) stressing the memory cell after setting the memory cell to the second state by asserting the wordline after initiating precharging of the pair of bitlines; and (d) determining the current state of the memory cell after stressing the memory cell to confirm whether the memory cell is still in the second state. While considered background with respect to our invention, this described application is co-pending and is incorported herein by reference.
In still another co-pending application by Aipperspach et al., is entitled xe2x80x9cStability Test for Silicon on Insulator SRAM Memory Cells Utilizing Disturb Operations to Stress Memory Cells Under Testxe2x80x9d, filed Apr. 19, 2000, Ser. No. 09/552,119 and assigned to IBM, which describes an apparatus, program product, and method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) to introduce switching history effects to a memory cell under test to stress the memory cell such that a reliable determination of stability may be made. There it was stated that it has been found that the worst case scenario for memory cell stability typically occurs immediately after a memory cell is switched to one state after the memory cell has been maintained in the other, opposite state for a period of time sufficient to introduce switching history effects. As such, a testing process may be configured to maintain a memory cell in a particular state for a period of time sufficient to introduce switching history effects, whereby the memory cell may be adequately stressed during the testing process to highlight any stability problems by setting the memory cell to an opposite state, and then shortly thereafter disturbing the memory cell, e.g., via a read to the memory cell or another memory cell on the same column or row of a memory array.
The co-pending application by Aipperspach et al., entitled xe2x80x9cStability Test for Silicon on Insulator SRAM Memory Cells Utilizing Disturb Operations to Stress Memory Cells Under Testxe2x80x9d, filed Apr. 19, 2000, Ser. No. 09/552,119 describes a method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) comprising: (a) introducing switching history effects to an SOI SRAM memory cell by maintaining the memory cell in a first state for a period of time; (b) setting the memory cell to a second state after introducing the switching history effects; (c) disturbing the memory cell after setting the memory cell to the second state; and (d) determining the current state of the memory cell after disturbing the memory cell to confirm whether the memory cell is still in the second state. While also considered background with respect to our invention, this described application is co-pending and is incorported herein by reference.
An improved test using a new reset test circuit is described herein below.
Described is a method for testing SOI technology memory circuits, such as in SRAMs, for weak SOI cells, using a reset test circuit with a wordline pulse width control circuit which can be implemented without performance impact and allows using unused silicon to minimize area usage impact and permits screening of integrated SOI memory array circuits for weak SOI cells using the test reset circuit which allows using a clock signal to reset the circuits being tested at the end of each clock cycle.
The method includes causing a selected circuit of an integrated SOI memory array circuit having a plurality of memory cells, each memory cell having a word select path and a bit select path to activate a reset path test circuit having a word select path and a bit select path which provide independent timed paths and having a pass gate multiplexer and a clock to reset the circuits being tested at the end of each clock cycle to test the SOI memory array memory cells by selectively changing signals passing through said reset test circuit to provide a wordline pulse width signal for a word select path with a reduced time while the memory cell bit path select and write signals turn off at normal times to stress the cell write margin.
Further, during test, the word line pulse width can be extended by blocking the reset signal with the wordline control circuit to produce a longer than normal pulse width. In addition, during a test for normal operations the reset signal is allowed to pass through the pass gate multiplexer of the wordline control circuit.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.